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A6850 Dual Channel Switch Interface IC

Features and Benefits
4.75to26.5Voperation LowVIN-to-VOUT voltage drop 1/ current sense feedback 10 Surviveshort-to-batteryandshort-to-groundfaults Survive40Vloaddump >4kVESDratingontheoutputpins,>2kVonallotherpins Outputcurrentlimiting LowoperatingandSleepmodecurrents IntegrateswithAllegroA114xandA118xHalleffect two-wire sensors
Description
The Allegro(R) A6850 is designed to interface between a microprocessor and a pair of 2-wire Hall effect sensors. The A6850 uses protected high-side low resistance DMOS MOSFETs to switch the supply voltage to the two Hall effect devices. Each switch can be controlled independently via individual ENABLE pins and both switches are protected with current-limiting circuitry. The output switches are rated to operate to 26.5 V and will source at least 25 mA per channel before current limiting. Typical two-wire Hall sensor applications require the user to measure the supply current to determine whether the Hall sensor is switched on (magnetic field present) or switched off (no magnetic field present). This is usually accomplished by using an external series shunt resistor and protection circuits for the microprocessor. In many systems, the sensed voltage is used as the input to a microprocessor analog-to-digital (A-to-D) input. This provides the system with an indication of the status of the two-wire switch as well as provides the capability for diagnostic information if there is an open or shorted sensor.
Package: 8 pin SOIC (suffix L)
Approximate Scale 1:1 Continued on the next page...
Functional Block Diagram
VIN ENABLE1
Control Block
ENABLE2
SENSE1 1/ 10
x IOUTPUT1
Fault Detection
OUTPUT1
SENSE2 1/ 10
x IOUTPUT2
Fault Detection
OUTPUT2
GROUND
6850-DS
A6850
Description (continued) The A6850 eliminates the need for the external series shunt resistor in Hall sensor applications by incorporating an integrated current mirror which reports the Hall sensor supply current as a 1/10 value on the SENSE1 or SENSE2 output pin. A low current Sleep mode
Dual Channel Switch Interface IC
is available (<15 A) by driving both ENABLE pins low. Also, the A6850 can be used to interface to mechanical switches. The A6850 is supplied in an 8-pin Pb (lead) free SOIC package, with 100% matte tin leadframe plating.
Selection Guide
A6850KLTR-T A6850KL-T
Part Number
Packing
13-in. reel, 3000 pieces/reel Tube, 98 pieces/tube
Absolute Maximum Ratings
Characteristic Supply Voltage Output Voltage SENSEx Voltage Range ENABLEx Voltage Range Operating Ambient Temperature Maximum Junction Temperature Storage Temperature ESD Rating - Human Body Model ESD Rating - Charged Device Model Symbol VIN VOUTPUTx VSENSEx VENABLEx TA TJ(max) Tstg HBM CDM AEC-Q100-00; OUTPUT1 and OUTPUT AEC-Q100-00; all other pins AEC-Q100-011; all pins Range K Notes Rating 40 -0.3 to 40 -0.3 to 7 -0.3 to 7 -40 to 15 150 -55 to 150 4.5 .5 1050 Units V V V V C C C kV kV V
Pin-out Diagram
Terminal List Table
Name
ENABLE1
Number
1 3 4 5 6 7 8
Description
Digital input pulled to ground Sensed current output Digital input pulled to ground Sensed current output Chip power supply voltage Switchable voltage supply to sensor Ground reference Switchable voltage supply to sensor
ENABLE1
1 Control Switch
8
OUTPUT1
SENSE1 ENABLE SENSE VIN OUTPUT GROUND OUTPUT1
SENSE1
2
7
GROUND
ENABLE2
3
Switch
6
OUTPUT2
SENSE2
4
5
VIN
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface IC
ELECTRICAL CHARACTERISTICS at TJ = -40 to +150C (unless noted otherwise) Characteristics Symbol Test Conditions Supply Input Voltage Range VIN Operating mode, IOUTPUTx = 0 mA Sleep mode: Supply Input Quiescent Current IINQ ENABLE1 and ENABLE low VOUTPUT1 = VOUTPUT = 0 V Power-Up Time1 tON OUTPUTx Source Resistance RDS(on) IOUTPUTx = 0 mA OUTPUTx Leakage Current IOUTPUTQ VOUTPUTx = 0 V; disabled ISENSEx = (IOUTPUTx / 10) + ISENSE(ofs) ISENSE(ofs), IOUTPUT = mA to 0 mA SENSEx Output Current Offset ISENSEQ VSENSEx = 0 V; disabled VIN > 7 V SENSEx Voltage3 VSENSEx VIN < 7 V VENABLEH ENABLEx Input Voltage Range VENABLEL ENABLEx Input Hysteresis VENABLEhys At least one output enabled ENABLEx = .0 V ENABLEx Current IENABLE ENABLEx = 0.4 V OUTPUT Current Limit IOUTPUTM Reverse bias blocking: VIN = 4.75 V, OUTPUT Reverse Bias Current IOUTPUT(rvrs) VOUTPUT = 6.5 V Overvoltage Protection Threshold VOVP Rising VIN Overvoltage Protection Hysteresis VOVPhys Thermal Shutdown Threshold TTSD Temperature Increasing Thermal Shutdown Hysteresis TTSDhys
1Delay For
Min. 4.75 - - - - - -100 - 0 0 .0 - 150 - - 5.0 - 7.0 - - -
Typ. - - - - - - - - - - - - - 40 8.0 35.0 500 - .0 175 15
Max. 6.5 5.0 15 0 35 0 100 10 6 VIN - 1 - 0.4 350 100 0 45.0 750 33.0 - - -
Units V mA A s A A A V V V V mV A A mA A V V C C
from end of Sleep mode to outputs enabled. input and output current specifications, negative current is defined as coming out of (sourced from) the specified device pin. 3User to ensure that V SENSEx remains within the specified range. If VSENSEx exceeds the maximum value, the device is self-protected by an internal clamp, but not all parameters perform as specified.
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RJA Test Conditions* 4-layer PCB based on JEDEC standard 1-layer PCB with copper limited to solder pads Value 80 140 Units C/W C/W
*Additional thermal data available on the Allegro Web site.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A6850
Dual Channel Switch Interface IC
Functional Description
Thermal Shutdown (TSD)
The A6850 protects itself from excessive heat damage by disabling both outputs when the junction temperature, TJ , rises above the TSD threshold (TTSD). The outputs will remain off until the junction temperature falls below the TTSD level minus the TSD hysteresis, TTSDhys. TJ can be estimated by calculating the power dissipation (PD) of the A6850. To calculate PD: PD = VIN IINQ - VOUTPUT1 IOUTPUT1 - VOUTPUT2 IOUTPUT2 - VSENSE1 ISENSE1 - VSENSE2 ISENSE2 . PD = VIN IINQ + (VIN - VOUTPUT1 ) IOUTPUT1 + (VIN - VOUTPUT2 ) IOUTPUT2 + (VIN - VSENSE1 ) ISENSE1 + (VIN - VSENSE2 ) ISENSE2 . The temperature rise of the A6850 can be calculated by multiplying PD and the thermal resistance from junction to ambient, RJA . The formula for temperature rise, T, is: T = PD x RJA . (3) The RJA for an 8-pin SOIC (Allegro L package) on a onelayerboardwithminimumcopperareais140C / W. (More thermal data is available on the Allegro MicroSystems Web site.) The total junction temperature can be calculated by: TJ = TA + T , where TA is the ambient air temperature. (4) (2) (1) Example: Calculating the power dissipation and temperature rise, given: TA = 25C, VIN = 5 V, IINQ = 5 mA, IOUTPUT1 = IOUTPUT2 = 15 mA, VDropx = VIN - VOUTPUTx = 0.7V, ISENSEx = IOUTPUTx /10 = 1.5 mA, and RSENSE1 = RSENSE2 =2k. Then: PD = 5 V x 5 mA +0.7Vx15mA+[5V-(1.5mAx2k)]x1.5 mA +0.7Vx15mA+[5V-(1.5mAx2k)]x1.5 mA = 52 mW . T=52mWx140C/W=7.3C . Substitutinginequation4: TJ = 25C+7.3C = 32.3C .
Substituting in equation 3:
Output Current Limit
The A6850 limits the output current to a maximum current of IOUTPUTM. The output current will remain at the current limit until the output load is reduced or the A6850 goes into thermal shutdown. The high output current limit allows the bypass capacitor, CBYP , on the Hall sensor to charge up quickly. This allows a high slew rate on the VCC pin of the Hall sensor, ensuring that the sensor Power-On State will be correct. See the Applications Information section for schematic diagrams and power calculations.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A6850
Dual Channel Switch Interface IC
Output Faults
The A6850 withstands short-to-ground or short-to-battery of the OUTPUTx pins. In the case of short-to-ground, current is held to the current limit (IOUTPUTM). If VOUTPUTx>(VIN+0.7V)duringshort-to-battery,the A6850 monitors VOUTPUTx and disables the outputs. Because the protection circuitry requires a finite amount of time to disable the outputs, a bypass capacitor of 1 F is necessary on VIN. Although OUTPUTx sinks current into the A6850 in this state, the current is bled to ground and does not chargeup capacitors tied to VIN.
limits on the sense pin (see Electrical Characteristics table).
Sleep Mode
Low-leakage or sleep modes are required in automotive applications to minimize battery drain when the vehicle is parked. The A6850 enters sleep mode when both ENABLE pins are low. In sleep mode, the internal regulators and all other internal circuitry are disabled. When enabling an output, the part must first come out of sleep mode. Consequently, the wake-up time amounts to a propagation delay before the outputs turn on. Also, the ENABLE pins do not switch with hysteresis until the regulators stabilize. After the internal regulators stabilize, internal circuitry is enabled and the outputs turn on, as shown in figure 1. As long as one ENABLE pin is held high, the A6850 operates with hysteresis.
Overvoltage Protection
The A6850 has built-in overvoltage protection against a load dump on the supply bus. In the case of a load dump, or when VIN is connected to the battery supply bus and VIN rises above the overvoltage threshold, VOVP , the A6850 will shut off the outputs.
SENSE Pin Outputs
The A6850 divides the OUTPUTx pin current by 10 and mirrors it onto the corresponding SENSEx pin. Putting sense resistors, RSENSE , from these pins to ground will create a voltage that can be read by an ADC (analog-to-digital converter). The value of RSENSE should be chosen so that the voltage drop across the sense resistor (VRSENSE) does not exceed the maximum voltage rating of the ADC. For further protection of the ADC, an external clamping circuit, such as a Zener diode, can be used to clamp any transient current spikes that may occur on the output that would be translated onto the SENSE pins. The sense current is one tenth of the output current, plus an offset current. This offset current is consistent across the whole range of the output current. The sense current can be calculated by the following formula: ISENSEx = (IOUTPUTx / 10) + ISENSE(ofs) . (5) The sense resistor must also be chosen to meet the voltage
ENABLE VENABLEL > tON
RegOk VREG
OUTPUT
Figure 1. Activation Timing Diagram. Exiting Sleep mode via ENABLE signal to output waveform.
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A6850
Dual Channel Switch Interface IC
Applications Information
Two-Wire Sensor Interfacing
When voltage is applied to two-wire Hall effect sensors, current flows within one of two narrow ranges. Any current level not within these ranges indicates a fault condition.
Signal and Fault Table Condition OUTPUT Pin Short-to-Ground Logic High from Hall Sensor Short-to-Battery Logic Low from Hall Sensor* Thermal Shutdown OUTPUT Pin Open
*This
The following table describes some of the possible output conditions that can be monitored through the SENSE pins. Figure 2 is a typical application using the A6850 with dual Hall effect sensors.
Output Pin Current (mA) 5 to 45 1 to 17 0.0 to 6.9 0.0 0.0
Sense Pin Current (mA) .5 to 4.5 1. to 1.7 0.0 0. to 0.69 0.0 0.0
Sense Pin Voltage, Rsense= 1.5 k (V) 3.75 to 6.75 1.8 to .55 0 0.3 to 1.04 0 0
current range includes all A114x and A118x sensors.
VCC VIN Digital Output Digital Output Controller ADC ADC
VCC or VBAT
1 F 1 ENABLE1 3 ENABLE2
5 VIN
OUTPUT1
8
Wiring Harness
A6850 2 SENSE1 4 SENSE2 6
CBYP 0.01 F A114x or A118x
OUTPUT2 GROUND 7
RSENSE1 1.5 k
RSENSE2 1.5 k
CBYP 0.01 F A114x or A118x
Figure 2. Typical Application with 2-Wire Hall Effect Sensors
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A6850
Dual Channel Switch Interface IC
Mechanical Switch Interfacing
The A6850 can be used as an interface between mechanical switches, set in a switch-to-ground configuration, and a low voltage microprocessor. A series resistor must be placed in the circuit to limit current when the mechanical switch is closed, in order to prevent excessive power dissipation in the A6850. For example, to calculate the power dissipation in the A6850 drivingtwomechanicalswitcheswith1kseriesresistors, with VIN = 12 V, assume that the current limit for each of the outputs is set to the maximum value, IOUTPUTM (max) = 45mA.
A series resistor included in the circuit reduces power dissipation in the A6850. The voltage drop across the resistor would be: VRSERIES = VIN - VDrop1 =12V-0.7V = 11.3 V . The current is then limited to: IOUTPUT1 = VRSERIES / RSERIES =11.3V/1k (8) (7)
= 11.3 mA . When the mechanical switch is closed without a series resistor, the A6850 will be at the current limit. The full 12 V of the Power dissipation in the A6850 from this switch is much powersupplywilldropacrosstheA6850at45mAThepower lower: dissipation for one mechanical switch closed would be: PD1 = VDrop1 x IOUTPUT1 (9) PD1 = VDrop1 x IOUTPUT1 (6) =0.7Vx11.3mA =12Vx45mA =7.91mW. =540mW.
VCC VIN Digital Output Digital Output Controller Input1 Input2
VCC or VBAT
1 F 1 ENABLE1 3 ENABLE2
5 VIN
OUTPUT1
8
Wiring Harness RSERIES
A6850 2 SENSE1 4 SENSE2 6 RSERIES
OUTPUT2 GROUND 7
RSENSE1
RSENSE2
Figure 3. Typical Application with Mechanical Switches
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A6850
Dual Channel Switch Interface IC
Ganging SENSE1 and SENSE2
In certain applications both outputs may be read with a single ADC channel. The OUTPUTx loads are enabled by alternatively activating ENABLEx. In fact, both ENABLE1
and ENABLE2 may be activated simultaneously, with the SENSE1 and SENSE2 currents added together. For valid measurements the load resistor need only be selected so that VSENSEx remain within specification.
Vcc Vin
Vcc or Vbat Digital Output Digital Output
0.47F Enable 1 Enable 2 Vin Output 1
Controller
ADC R Sense 1 Sense 2
A6850
Output 2
VENABLE1 VENABLE2 IOUTPUT1 ILOAD1 ILOAD1
IOUTPUT2 VADC R*ILOAD1/10
ILOAD2 R*ILOAD2/10
ILOAD2
R*(ILOAD1/10 + ILOAD2/10)
LOAD2
LOAD1
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A6850
Dual Channel Switch Interface IC
L Package, 8-Pin SOIC
6.20 .244 5.80 .228 0.25 [.010] M B M 5.00 .197 4.80 .189 8 A B 8 0 0.25 .010 0.17 .007 Preliminary dimensions, for reference only Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only (reference JEDEC MS-012 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P600-8M);
4.00 .157 3.80 .150 A 1.27 .050 0.40 .016
adjust as necessary to meet application process requirements 1 2 0.25 .010 8X 0.10 [.004] C 8X 0.51 .020 0.31 .012 0.25 [.010] M C A B 1.27 .050 C SEATING PLANE GAUGE PLANE
SEATING PLANE 1.75 .069 1.35 .053 0.25 .010 0.10 .004
2.50 .098 REF
B
4.90 .193 REF
0.65 .026 MAX
1.27 .050 REF
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright(c)2006 AllegroMicroSystems, Inc. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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